A phase-locked loop (PLL) is a control system that generates an output signal having a phase that is related to the phase of an input reference signal. As PLLs are commonly used in clocked circuits, the input reference signal is often referred to as a reference clock. In its most straightforward form, a PLL comprises a phase-frequency detector (PFD), a loop filter, a voltage-controlled oscillator (VCO), and a frequency divider. The PFD compares the frequency of the input reference clock with the frequency of a feedback signal. The phase error signal resulting from this comparison is provided to the loop filter, which is commonly implemented as a charge pump, and the output of the loop filter drives the VCO. The output of the VCO serves not only as the output of the PLL but also as the aforementioned feedback signal.
A PLL design is characterized by, among other design parameters, a certain bandwidth and certain amount of peaking. The bandwidth of a PLL is a measure of the extent to which the PLL can track the input reference clock phase. A high-bandwidth PLL can achieve phase lock faster than a low-bandwidth PLL and can advantageously track jitter in the reference clock. A low-bandwidth PLL filters jitter in the input reference clock to a greater extent than a high-bandwidth PLL but takes longer to achieve phase lock than a high-bandwidth PLL. As illustrated by the exemplary phase transfer function 10 shown in FIG. 1, in the context of a PLL, “bandwidth” most commonly refers to the portion of the PLL frequency response between a minimum operational frequency and a frequency at which the frequency response falls 3 decibels (dB) below a peak frequency response 12. This point is commonly referred to as the “3 dB point,” and the PLL bandwidth may alternatively be referred to as the 3 dB bandwidth. Note in FIG. 1 that the PLL output phase accurately tracks the reference clock phase over a substantial range of frequencies, but at frequencies above peak frequency response 12, the magnitude of the PLL output phase signal becomes increasingly attenuated with further increase in frequency. In the context of a PLL, the term “peaking” refers to a measure of the extent to which the peak frequency response 12 exceeds the frequency response over the range of frequencies at which the PLL output phase accurately tracks the reference clock phase.
A dual-path PLL is similar to the above-described single-path PLL, but the PFD output is provided to two paths: a proportional path and an integral path. Each path has a separate loop filter. The VCO combines the outputs of the two paths. Each loop filter (charge pump) can be tuned or adjusted. The PLL bandwidth or 3 dB point can be set by adjusting the proportional path gain. The amount of PLL peaking can be set by adjusting the integral path gain.
Semiconductor fabrication process tolerances are so wide that it is difficult to fabricate a PLL having desired or target values of bandwidth and peaking. Calibration techniques have been used in attempts to more accurately set such PLL parameters to desired or target values.